The present invention relates to semiconductor integrated circuits (IC's), and more particularly to back-end-of-the-line (BEOL) interconnects structures.
The continuous scaling to smaller dimensions and the introduction of low-k dielectrics in copper interconnects have caused reliability issues to become a greater concern in addition to increasing process complexity. In semiconductor interconnect structures Electromigration (EM) has been identified as a metal failure mechanism. EM is a serious reliability concern for very large scale integrated (VLSI) circuits.
Electromigration failure along the Cu/dielectric interface has been identified as a major reliability concern for VLSI circuit applications. It has been observed that voiding in the metal line with the mass transport in the Cu line occurring along the interface of the dielectric, for example Si3N4, SiC, and SiC(N,H), capping layer and Cu. Reducing Cu transport and atomic voiding at the Cu/dielectric interface is a major objective in the semiconductor industry for reliability enhancement.
FIG. 1 is a cross sectional view of a conventional interconnect structure. A copper interconnect 10 is formed in an inter level dielectric (ILD) material 20. A compressive capping layer 30 is then formed over the exposed surface of the interconnect structures 10 and ILD 20. In the conventional interconnect structure shown in FIG. 1, a single compressive capping layer 30 is provided with a single CVD deposition step. The compressive capping layer is deposited with a typical thickness of approximately 250 Å. The compressive capping layer in this case results in a tensile stress within the Cu interconnect. The CVD deposition parameters are typically at a pressure of approximately 2.4 Torr, temperature of approximately 400° C., and HF power of approximately 1,170 Watts, LF power of approximately 130 Watts. The gas composition and flow rates are typically SiH4 at approximately 250 standard cubic centimeters per minute (sccm), N2 at approximately 19,000 sccm, and NH3 at approximately 1,300 sccm.
Reducing Cu transport and atomic voiding at the Cu/dielectric interface is disclosed in the present invention by creating compressive stresses in the Cu interconnect. In contrast to a Cu interconnect in the prior art with tensile stress, a Cu interconnect with high compressive stress results in better resistance to electromigration effects. It is also disclosed in the present disclosure that depositing a tensile film on top of the Cu interconnect and/or depositing a compressive film around the Cu interconnect results in high compressive stress in the Cu interconnect, which is beneficial for improving EM resistance in the Cu interconnect.
Therefore, an object of the present invention is to provide a high tensile stress capping layer on top of the Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.